In spread spectrum communications, there must be compensation in signals like processing for errors due to fading in the received signals.
FIG. 5 shows such signals, in which known pilot signals P1 and P2 (signals with a plurality of bits, for example, Np bits) are input before and after the predetermined quantity of information signal S(t) (a signal with a plurality of bits). According to these pilot signals, phase errors caused by fading are presumed with respect to the signals between the pilot signals, and compensated. Here, assuming that the pilot signals are (P1.sup.(k) i+j.multidot.P1.sup.(k) q) and (P2.sup.(k) i+j.multidot.P2.sup.(k) q), each information signal symbol is (Di+j.multidot.Dq), P1.sup.(k) and P2.sub.(k) with bits P1 and P2, respectively, being averaged by averaging circuits A1 and A2, and all the pilot signals in the send mode are (1+j.multidot.0) (other patterns can be adopted), the average value E of information signal error vectors is expressed by formulas (1) to (5): ##EQU1##
Compensating vector M according to the formulas above is given by a complex conjugate number. P1i, P1q, P2i and P2q are the average values of the pilot signal trains, which reduce the influence of noise. The compensation coefficient is calculated by formula (6): ##EQU2##
Multiplying the value of formula (6) by each information signal symbol, compensates the influence of fading. When Dc stands for the compensated information symbol, it is calculated by formula (7): EQU Dc=D.multidot.M=(Di+j.multidot.Dq)(Mi+j.multidot.Mq)=(Di.multidot.Mi-Dq.mul tidot.Mq)+j.multidot.(Dq.multidot.Mi+Di.multidot.Mq) (7)
Assuming the in-phase components and the quadrature components after the compensation of N numbers of paths to be Dci1 t o DciN and Dcq1 to DcqN, respectively, the in-phase components Dci and quadrature components Dcq of signals after rake composition are calculated by accumulations of signals in each path as in formulas (8) and (9): ##EQU3##
FIG. 6 shows the phase compensating circuit COR for performing each processing above. In FIG. 6, receiving signal Sin undergoes proper timing adjustment and is input to two pilot signal holding circuits SHP1 and SHP2 and information signal holding circuit SHS. Each bit P1(k) and P2(k) of P1 and P2 held by SHP1 and SHP2, respectively, is averaged by averaging circuit A1 and A2, respectively, and pilot signals P1 and P2 are calculated. Compensation coefficient calculating circuit MC calculates compensation coefficient M according to these pilot signals. Compensation coefficient M is input to multiplication circuit MUL, multiplied by information signal D, and the signal Dck is output after compensation.
FIG. 7 shows a rake processing circuit which also performs phase compensation of a plurality of paths (four paths in FIG. 7 as an example). First, multipath signals greater than a predetermined level are selected among the input signals by multipath selecting circuit MULSEL. The selected signals are input to compensation circuits COR1 to COR4, arrayed in four phases corresponding to the first to the fourth paths, respectively. Their outputs are then input to accumulating circuit .SIGMA. after being appropriately delayed by delaying circuits D1 to D4, respectively. Outputs SCs of .SIGMA. correspond to Dci and Dcq above.